AC performance, part 2. Input capacitance modulation. Load influence.

Modulation of Input Capacitance.

Changing offset causes some changes in the frequency response. While AC analysis is small signal analysis, offset change will show some differences in big signal performance. One part of this change is modulation of Ccb capacitance.

This capacitance could be estimated, using the following formula:

Where Cjc is collector junction capacitance at 0 junction voltage, Vcb is actual collector-base junction voltage,  Vjc and Mjc are transistor specific voltage and coefficient. They should be taken from corresponding SPICE model. Common range for Vjc is 0.5-07V and for Mjc is 0.3-0.5.

Attached Excel spreadsheet demonstrates this capacitance change in case of topology 1 (schematic 1) while input voltage is changing from 0 to 30 volts. It is also shown in the following picture as Ccb_sum.

Ccb modulation Vs. input voltage

This change of Ccb modulates the frequency response. You can see that different versions of input stage show different susceptibility to this effect. The first one (red plot) is the worst, because it has the biggest change in collector base voltage.  While capacitance change in complementary stage is partially compensated, it is a recognizable change anyway.

Frequency response modulation with change of input voltage due to Ccb change

Frequency response modulation with change of input voltage due to Ccb change

Possible ways to address this change is to use input transistor with small Ccb. The other way is to increase supply voltage, increasing Vps/Vin ratio. This is not the best solution, because it makes power stage less efficient and increases power dissipation. One more way is to increase value of input capacitance, connected in parallel with Ccb. It is also not very good solution, because it strongly affects bandwidth of output stage.

More attractive solution seems to be using special input buffer, with almost no change of Vcb voltage. This will keep Ccb nearly constant and minimize modulation. Some other sources, like similar Ccb change in following stages will exist, but they are making much less influence, because they are driven from much less impedances.

This solution is implemented in topologies 2, 3 and 4.

Let’s evaluate cutoff frequency change for all versions of output stages while input signal (offset) changes from 0V to 35V.

The other interesting measure is modulation of phase shift with the same input signal change (0 to 35V).

Test frequency is 20 KHz.

As you can see, topologies 2, 3 and 4 show big advantages over topology 1 in both tests.

While these results are interesting, they are hard to interpret in terms of how good these numbers should be to make a perfect design. The other aspect of these kinds of tests- they should be performed on the whole amplifier, not just the output stage.

For example, VAS output stage is sensitive to the same type of problems. In general, any stage with big signal amplitudes could be prone to the same type of modulation. Most of commonly used VAS outputs will produce very similar to output stage topology 1 amount of modulation. In this case, best and worst output stages will differ by only 2x, considering VAS together with the output stage. Improving VAS performance in this aspect could be a challenge and is out of our scope for now.

Load influence.

Next set of tests is related to change of small signal transfer function, while driving different loads. Two loads, 8 Ohm and 2 Ohm were selected. While 2 Ohms may seem to be extremely low, many 4 Ohm loudspeakers may have impedance, close to 2 Ohm at some frequencies. The other reason is to emphasize potential problems (if any), common to particular topology.

Let’s evaluate performance of all topologies at 1 KHz first. Offset voltage is 0 V:

And with offset voltage of 35 V:

For 20 KHz with 0V offset results will look like:

Results for 20 KHz with 35V offset:

 

Output impedance.

Results of previous tests show importance of output impedance evaluation. Small signal AC voltage source was inserted between load and ground to inject test signal. Output impedance was evaluated as ratio between voltage at the output and current in the load, while making AC sweep of added voltage source.

Results are represented in the following picture. It shows 2 set of curves, with 0V offset and with offset 35V.

Output impedance, 0 and 35V offset

Separate curves with offset 0V are on the next picture.

Output impedance 0v offset

Separate curves with offset 35V are on the next picture.

Output impedance, 35v offset

The last picture shows low frequency portion of the first one, 0 and 35V results together in zoomed form.

Output impedance, 0 and 35v offset, LF zoom

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