Subcircuit structure

  1. Header
  2. Netlist
  3. End

Subcurcuit definitions in LTSPICE are stored in text files with extension .lib or .sub.

Each .lib file may contain one or more subcircuit definitions.

Subcircuits may contain:

  • Basic circuit elements
  • Other subcircuit definitions
  • Device models
  • Calls to subcircuits defined internally or externally

Subcircuit has the following structure:

  • Header – subcircuit name, pinout and parameter descriptor – if you want to pass some parameters from main SPICE circuit to subcircuit
  • Schematic in the form of netlist
  • Model’s descriptions, if any
  • End statement

Subcircuit header

.SUBCKT Name  Pinname1  Pinname2… PinnameN PARAMS: Param1 Param2 … ParamM


.SUBCKT is SPICE directive, stating that this is the beginning of subcircuit description

Name is subcircuit name

PinnameN – name assigned to the Nth pin. N (pin number in subcircuit header) should be the same as netlist number of corresponding pin in symbol drawing. In LTSPICE subcircuit PinnameN is the name that is used in internal to subcircuit  netlist  What really matters for external connection is the order of names. First name has N=1, second name has N=2 and etc. When LTSPICE will establish connection between subcircuit and the part drawing, Pinname1 in subcircuit header will correspond to pin number 1 in the part drawing, Pinname2 will correspond to pin number 2 and etc.  PinnameN could not be 0. Zero has special meaning – it is ground. You may use any other name (including numbers, other than 0) for the pin that will be connected to ground on schematic.

PARAMS: separator between pin names and parameter declaration



Pin names and parameters are separated by space

Parameters could also be declared in subcircuit body by using .param SPICE directive


.param Rp=1K

.param R_OUT={GAIN/Gm}

The parameter must be enclosed within curly braces { } while it is used in the subcircuit.

Parameter value could be entered from the schematic and could be stepped during simulation. If parameter value is not specified in schematic, default values are used.

{ } braces have a meaning of parameter value.



Rp 1 2 {Rp}

G_OUT 0 OUT 2 0 {Gm}

Rules For Curly Braces { }

  • Curly braces are necessary if used as values for resistors, capacitors, inductors, E, F, G, H, V, I -sources, or parameters of “.models“. Curly braces have to include the whole expression here.
  • They are optional for behavioral sources, “.function” and “.param” statements.
  • If used in “.param” then curly braces must be around the whole expression.
  • If used in “.function” then curly braces must be around the whole expression.
  • In B-sources (behavioral sources) they can be around the static (independent) values, but not around dependent voltages or currents.
  • In “.measurePARAM …” no braces are allowed even when params are referenced.

Example of subcircuit header




amp – is subcircuit name

IN_PLUS – is the name of pin 1

IN_MINUS – is the name of pin 2

OUT – is the name of pin 3

Gm=1m – is the name and value of first parameter

GAIN=100K – is the name and value of second parameter

+ sign in front of GAIN=100K means that the previous line is continued on the next line and it is still part of subcircuit header

And if {Gm} would be used later in subcircuit definition, it will have the same meaning as 1m or 1 millisiemens as soon as this value is assigned in subcircuit header


Subcircuits are using the same set of components, that every SPICE circuit is using. Netlist specifies connections of these components.

Any device model or subcircuit definition included in a subcircuit netlist are local (these models and definitions are not known/visible outside the subcircuit definition).

Any circuit nodes not included on the .SUBCKT line are local with one exception: Spice defines node 0 (zero) as circuit ground in both circuits and subcircuits. Node 0 is always “global”.

Circuit nodes may be identified with either numbers or letters.

Netlist building blocks:


Line, starting with * represents comments. You can also use ; for comments. Comments make your netlist more readable and easier to support.

Device Models

Some standard devices, included in SPICE, require big list of parameters to specify their behavior.  Set of device model parameters for these devices is specified in .model statement.

.model modelname modeltype (Par1=Pval1 Par2=Pval2 … )

Model parameters that are not specified inside the braces are assigned their default value.


.model Switch11 SW(Ron=.1 Roff=1Meg Vt=0 Vh=-.5 Lser=10n Vser=.6)

The model name must be unique. That is, two different types of circuit elements, such as a diode and a transistor, cannot have the same model name. The parameter list depends on the type of model.

List of model types
SW Voltage Controlled Switch
CSW Current Controlled Switch
URC Uniform Distributed RC Line
LTRA Lossy Transmission Line
D Diode
NPN NPN Bipolar Transistor
PNP PNP Bipolar Transistor
NJF N-channel JFET model
PJF P-channel JFET model
NMF N-channel MESFET
PMF P-channel MESFET
VDMOS Vertical Double Diffused Power MOSFET


Major LTSPICE components, elementary devices:

R – resistor

Rxxx n1 n2 <value> [tc=tc1, tc2, …] [temp=<value>]

R=Rnominal*(1+tc1*(T – Tnominal)+tc2*(T – Tnominal)2+…)

C – capacitor

Cnnn n1 n2 <capacitance> [ic=<value>][Rser=<value>]

+[Lser=<value>] [Rpar=<value>] [Cpar=<value>] [m=<value>]

+ [RLshunt=<value>]

m is the number of parallel units, ic is initial voltage


Equivalent circuit of capacitor

Equivalent circuit of capacitor

C – non linear capacitor (does not exist in SPICE3)

Cnnn n1 n2 Q=<expression> [ic=<value>] [m=<value>] (LTSPICE only)

Q is the charge

x is a special variable, meaning voltage across capacitor


Cnnn n1 n2 Q=100p*x – has meaning of 100p capacitance, because Q=C*V

Vcap n1 n2 4 ( x=4 in this example)

Cnnn n1 n2 Q=x*if(x<0,100p,300p) – C=100p for V<0; C=300p for V>=0

L – inductor

Lxxx n+ n- <inductance> [ic=<value>] [Rser=<value>] [Rpar=<value>]

+ [Cpar=<value>] [m=<value>] [temp=<value>]

m is the number of parallel units, ic is initial current


Inductor equivalent circuit

Inductor equivalent circuit

L – nonlinear inductor –  may be of 2 different types

One is a behavioral inductance specified with an expression for the flux, the other is based on hysteretic core model.

K – coupled (mutual) inductors

Kxxx L1 L2 […Ln] coefficient

L1, L2, …Ln are the names of coupled inductors in the circuit.

coefficient is the mutual coupling coefficient and must be in the range of -1 to1.

Some other devices are:

O – lossy transmission line

T – lossless transmission line

U – uniform RC line

Major LTSPICE components, semiconductor devices

D – diode

Dnnn n1 n2 diodename [area] [off] [m=<val>] [n=<val>] [temp=<value>]

n1 – node name for anode

n2 – node name for cathode

diodename – name of diode model, described in following .model statement

area – the area factor. The area factor used on the diode, BJT, JFET, and MESFET devices determines the number of equivalent parallel devices of a specified model. If the area factor is omitted, a value of 1.0 is assumed

off – optional starting condition on the device for dc analysis

m sets the number of parallel devices, LTSPICE enhancement

n sets the number of series devices, LTSPICE enhancement


D14 in out Mydiode

.model Mydiode D(Ron=.1 Roff=1Meg Vfwd=.4)

Q – bipolar junction transistors (BJTs)

Qnnn nc nb ne [ns] modelname [area] [off] [IC=<Vbe, Vce>] [temp=<T>]

nc, nb, ne – node names for collector, base and emitter

ns – node name for substrate. If unspecified, substrate is connected to ground

modelname – name of BJT model, described in following .model statement


Q23 1 12 30 2n3904

.model 2n3904 NPN(IS=1E-14 VAF=100 Bf=300 IKF=0.4 XTB=1.5 BR=4 CJC=4E-12 CJE=8E-12 RB=20 RC=0.1 RE=0.1)

NPN or PNP before (…)  specifies polarity of your model


LTspice contains seven different types of monolithic MOSFET’s and one type of vertical doubly diffused Power MOSFET.

LTspice supports MOSFET level 1, 2, 3, 4, 5, 6, 8, 9, 12, 14. The default level is 1

Mxy nd ng ns nb modelname [m=<value>] [L=<len>] [W=<width>]

+[AD=<area>] [AS=<area>] [PD=<perim>] [PS=<perim>] [NRD=<value>]

+[NRS=<value>] [off] [IC=<Vds, Vgs, Vbs>] [temp=<T>]

nd, ng, ns, nb – node names for drain, gate, source, and bulk (substrate) nodes

modelname – name of MOSFET model, described in the following .model statement

Model definition example:

.model modelname NMOS (LEVEL=1 IS=1e-32 VTO=3.00977 LAMBDA=0

+KP=209.826 CGSO=1.8488e-05 CGDO=1.056e-06)

NMOS and PMOS specify a monolithic N or P channel MOSFET transistor.

The keyword VDMOS (LTSPICE only) specifies a vertical doubly diffused power MOSFET.

Mxxx Nd Ng Ns <model> [L=<len>] [W=<width>] [M=<area>] [m=<value>] [off] [IC=<Vds, Vgs, Vbs>] [temp=<T>]


M1 Nd Ng Ns Si4410DY

.model Si4410DY VDMOS(Rd=3m Rs=3m Vto=2.6 Kp=60 Cgdmax=1.9n Cgdmin=50p Cgs=3.1n Cjo=1n Is=5.5p Rb=5.7m)

J – JFET transistor

Jnn D G S modelname [area] [off] [IC=Vds, Vgs] [temp=T]


J1 out in 5  jfetname

.model jfetname NJF(Lambda=.001)

J2 dr in out fetname

.model fetname PJF(Lambda=.001)

Z – MESFET transistor

Zxxx D G S modelname [area] [off] [IC=<Vds, Vgs>] [temp=T]

Major LTSPICE components,  more devices

S – Voltage Controlled Switch

Sname n1 n2 nc+ nc- modelname [on,off]

W – Current Controlled Switch

Wname n1 n2 Vname modelname [on,off]

Major LTSPICE components,  voltage and current sources

V – Voltage Source

Vname n+ n-  voltage [AC=<amplitude>] [Rser=<value>] [Cpar=<value>]

I – Current Source

Iname n+ n-  current [AC=<amplitude>] [load]

If the source is flagged as a load, the source is forced to be dissipative, meaning that the current goes to zero if the voltage between nodes n+ and n- goes to zero or a negative value.

E – Voltage Dependent Voltage Source

Ename n+ n-  nc+ nc-  gain

This means that input voltage, applied between nc+ nc– sets output voltage between n+ n– with coefficient of proportionality = gain

Ename n+ n-  nc+ nc-  table=(value pair,  value pair , …)

A look-up table is used to specify the transfer function. The table is a list of pairs of numbers. The second value of the pair is the output voltage when the control voltage is equal to the first value of that pair. The output is linearly interpolated when the control voltage is between specified points. If the control voltage is beyond the range of the look-up table, the output voltage is extrapolated as a constant voltage of the last point of the look-up table.

Behavioral voltage source:

Ename n+ n- value={expression}

F – Current Dependent Current Source

Fname n+ n-  Vname  gain

The output current is equal to the value of the gain times the current through the voltage source specified as Vname.

G – Voltage Dependent Current Source

Gname n+ n-  nc+ nc-  gain

Input voltage, applied between nc+ nc- sets output current between n+ n- with coefficient of proportionality = gain

Gname n+ n-  nc+ nc-  table=(value pair,  value pair , …)

A look-up table is used to specify the transfer function.

H – Current Dependent Voltage Source

Hname n+ n-  Vname gain

The output voltage is equal to the value of the gain times the current through the voltage source Vname.


B – Arbitrary behavioral voltage or current sources

Behavioral voltage source

Bnnn n001 n002 V=expression [ic=value] [tripdv=value] [tripdt=value] [laplace=expression [window=time]

+ [nfft=number] [mtol=number]]

Behavioral current source

Bnnn n001 n002 I=expression [ic=value] [tripdv=value] [tripdt=value] [Rpar=value] [laplace=expression

+[window=time] [nfft=number] [mtol=number] ]

Major LTSPICE components, Special Functions

Annn n001 n002 n003 n004 n005 n006 n007 n008 model [instance parameters]

These are Linear Technology Corporation’s proprietary special function/mixed mode simulation devices. Most of these and their behavior are undocumented.

Some of devises are idealized behavioral logic gates. INV, BUF, AND, OR, and XOR are supported. For this logic devices, pins 1 to 5 are inputs, 6 and 7 are complementary outputs and 8 is common (not necessarily ground). Unused pins should be connected to pin 8.

This group of devices also include VARISTOR (voltage controlled varistor with breakdown voltage set by the voltage between terminals 1 and 2) and MODULATE (voltage controlled oscillator)

Expressions and functions in LTSPICE subcurcuits

Expressions can contain the following:

  • Node voltages, e.g., V(n001)
  • Node voltage differences, e.g., V(n001, n002)
  • Circuit element currents, for example, I(S1), the current through switch S1 or Ib(Q1), the base current of Q1.

It is assumed that the circuit element current is varying quasi-statically, that is, there is no instantaneous feedback between the current through the referenced device and the behavioral source output.


Supported Functions are: abs(x); acos(x); acosh(x); asin(x); asinh(x); atan(x); atanh(x); cos(x); cosh(x); exp(x); ln(x); log10(x); sgn(x); sin(x); sinh(x); sqrt(x); tan(x); tanh(x); int(x); floor(x); rand(x); min(x,y); max(x,y); limit(x,y,z); … and many other mathematical, logical or signal processing functions.

.ENDS – Specifies end of Subcircuit Definition


2 Responses to Subcircuit structure

  1. Beatriz Pês says:

    Hi! I’m trying to do a AND gate with a lookup table in ltspice iv. I’m new with it so i’m unsure about the syntax. Is it possible to do a lookup table with more than one input? All the examples that i find use only one input and one output.

  2. Dave Blanchard says:

    I am trying to do a lookup table with 100 pairs in the table. What is the table pair limit and how can one reference a table from Excel?