Accurate TL431 model development, analysis and evaluation

I used datasheet schematic to create a model for TL431. This is very similar to Helmut Sennewald’s approach and seems to be straight-forward way of developing model, while schematic is available and is not very complicated. However, schematic is just a starting point. There is a big difference between board level design with discrete components and chip design. While designing with discrete components, board level designer tries to avoid influence of not very stable parameters (or parameters with big possible deviation) on board parameters. This is usually done by wide usage of passive components and selection of solutions that do not strongly depend on semiconductor parameters (like BJT betta, Vbe/Ic variations, etc.). On the other hand, chip designers are limited in passive component selection, but can vary process parameters and device geometry to create semiconductor devices with desired parameters. This means that chip schematic will require very accurate representation of components, used to achieve desired performance. If you will try to use some generic “one fits it all” transistor for the chip, you may end up with not very accurate model for the part.

Following schematic represents suggested model.

TL431ED Model Schematic

TL431ED Model Schematic

It was necessary to adjust parameters of transistors to get desired level of model accuracy. I don’t know parameters of transistors, used in this chip design. I empirically adjusted some of model parameters to get the best match between model and chip performance. Basic transistor parameters influencing model performance are specified in .MODEL statement. In addition to this, it was essential to control current distribution between Q2 and Q3 transistors (and some others). This adjustment highly influences accuracy of DC performance. In general, current flow through transistor is highly affected by Is (transport saturation current) model parameter.  You can use separate .MODEL statement for every transistor that requires other than default value (Is=1e-16) of transport saturation current. Or you can use “area” parameter to scale device currents. It was more convenient to use “area” parameter with the same .MODEL statement for transistor.

Some other component values were adjusted for better match to performance specifications.

TL431 model was created in the form of hierarchical block TL431ED.asc to be used together with TL431ED.asy schematic symbol.

You can also use subcircuit version of this model TL431ED.sub together with TL431.asy symbol. TL431ED Subcircuit can be easily integrated in any SPICE compatible simulation software.

Attached file TL431.zip contains all necessary LTSPICE model files for TL431 together with Test Bench schematics, used to verify and compare recently created and other models performance.

Test Bench results will be discussed in the next section.

Comments

One Response to Accurate TL431 model development, analysis and evaluation

  1. TeeHowe Peh says:

    Hi Eugene,

    Thank you for this really useful spice model. I do have questions on how did you come up with the following spice parameters? Thanks!

    .model QN_ED NPN(BF=140 Cje=1p Cjc=2p Rb=40 VAF=80 VAR=50 KF=3.2e-16 AF=1)
    .model QP_ED PNP(BF=60 Cje=1p Cjc=3p Rb=80 VAF=70 VAR=40)
    .MODEL D_ED D(Rs=5 CJ0=4.0p)