AC small signal gain, 8 Ohm load.
Overall gain for all 4 stages was evaluated on the following plots.
We will try to use similar colors for all comparison testing.
1 – RED
2 –BLUE
3 – YELLOW
4 -GREEN
AC performance comparison
I was not very happy with high frequency peaking of stage 4. Stage 4 was modified after some experiments to reduce amount of peaking.
Updated schematic of stage 4
Updated AC performance plots
Low frequency portion of transfer function is represented on the next plot
Low frequency portion of transfer function
What these plots show:
Low frequency gain is -1.5dB for stage 1, -0.27dB for stages 2 and 4, -0.5 dB for stage 3.
Dominant poles for all 4 stages are mostly determined by VAS load. It is 500 Kohm resistor and 20 pf capacitor, leading to 15.9 Khz cutoff frequency. Stage 1 shows more influence of input transistor collector-base capacitance, resulting in 15.2 Khz cutoff frequency. Though, good characteristics of input transistors (2SC3503 and 2SA1381) and big voltage across collector-base junctions make this influence relatively small. Additional efforts to minimize collector-base capacitance influence are taken in all other stages, resulting in higher cutoff frequencies of 15.7 Khz for all other output stages.
Stages 2, 3 and 4 show some peaking at high frequency’s, especially stages 2 and 4. This is related to specifics of buffer stages and, in some cases, may cause oscillation. Though, this should not be a problem and with some attention to the phenomena, could be easily fixed.
Other two plots of interest are input impedance of all 4 stages (VAS load 500 Kohm and 20 pf is not included) and Voltage Amplifier Stage (VAS) load. The first one (input impedance) is taken as stage input voltage divided buy sum of input currents (base currents of input transistors).The second one (VAS load) represents total load, basically it is the first one in parallel with passive RC at VAS output.
Input Impedance
VAS Load
First plot is more interesting as soon as any changes on the second one are masked to the high degree by impedance of passive RC load itself. You may see that stage 3 have much higher (on the order of magnitude) input impedance than stage 1. And stages 2 and 4 have input impedance even higher than stage 3. While you may question the necessity of this high impedance, it is obvious that proportional changes of input impedances will result in smaller variation of VAS load in case of higher impedances. And smaller changes in VAS load mean less distortions.
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